The present invention relates to a demodulating apparatus of a receiver, and more specifically to a demodulating apparatus of a receiver for demodulating a PSK modulated signal obtained by time-multiplexing a digital signal modulated in a 2-phase, 4-phase, and 8-phase PSK modulation system in a hierarchical transmission system, etc. by using a carrier regenerated by carrier regeneration means, and outputting an I-Q symbol stream data.
A digital satellite TV broadcast in a plurality of modulation systems in which different necessary C/Ns are required, for example, in a hierarchical transmission system in which an 8 PSK modulated wave, a QPSK modulated wave, and a BPSK modulated wave are time-multiplexed and repeatedly transmitted for each frame has been developed for practical use.
FIG. 8 shows an example of the configuration of one transmission frame in the hierarchical transmission system. One frame includes a frame synchronous signal pattern (predetermined 20 symbols are actually used as a frame synchronous signal in 32 symbols) formed by 32 BPSK-modulated symbols, a TMCC (transmission and multiplexing configuration control) pattern for transmission multiplexing configuration identification formed by 128 BPSK-modulated symbols, a superframe identification pattern formed by 32 symbols (predetermined 20 symbols are actually used as a superframe identification signal in 32 symbols), a main signal having 203 8 PSK (trellis codec 8 PSK) modulated symbols, a 4-symbol burst symbol signal (BS) obtained by BPSK-modulating a pseudo random noise (PN) signal, a main signal having a 203 8 PSK (trellis codec 8 PSK) modulated symbols, a 4-symbol burst symbol signal (BS) obtained by BPSK-modulating a pseudo random noise (PN) signal, a main signal having 203 QPSK-modulated symbols, a 4-symbol burst symbol signal (BS) obtained by BPSK-modulating a pseudo random noise (PN) signal, a main signal having 203 QPSK-modulated symbols, and a burst symbol signal (BS) having 4 BPSK-modulated symbols in this order.
Here, the mapping for each modulation system on the transmission side will be described below by referring to FIGS. 9A-9C. FIG. 9A shows a signal point arrangement at the I-Q phase (an I-Q vector or an I-Q signal space diagram) when the 8 PSK modulation system is used. In the 8 PSK modulation system, a 3-bit digital signal (abc) can be transmitted as 1 symbol, and there can be 8 combinations of bits forming 1 symbol, that is, (0 0 0), (0 0 1), (0 1 0), (0 1 1), (1 0 0), (1 0 1), (1 1 0), and (1 1 1). These 3-bit digital signals are converted into the signal point arrangements 0 through 7 in the I-Q phase on the on the transmission side as shown in FIG. 9A. The conversion is referred to as 8 PSK mapping.
In an example shown in FIG. 9A, the bit string (0 0 0) is converted into the signal point arrangement xe2x80x980xe2x80x99, the bit string (0 0 1) is converted into the signal point arrangement xe2x80x981xe2x80x99, the bit string (0 1 1) is converted into the signal point arrangement xe2x80x982xe2x80x99, the bit string (0 1 0) is converted into the signal point arrangement xe2x80x982xe2x80x99, the bit string (1 0 0) is converted into the signal point arrangement xe2x80x983xe2x80x99, the bit string (1 0 0) is converted into the signal point arrangement xe2x80x984xe2x80x99, the bit string (1 0 1) is converted into the signal point arrangement xe2x80x985xe2x80x99, the bit string (1 1 1) is converted into the signal point arrangement xe2x80x986xe2x80x99, and the bit string (1 1 0) is converted into the signal point arrangement xe2x80x987xe2x80x99.
FIG. 9B shows the signal point arrangement at the I-Q phase when a QPSK modulation system is used. In the QPSK modulation system, a 2-bit digital signal (de) can be transmitted as 1 symbol, and there can be 4 combinations of bits as a symbol. They are (0 0), (0 1), (1 0), and (1 1). In the example shown in FIG. 9B, for example, the bit string (0 0) can be converted into the signal point arrangement xe2x80x981xe2x80x99, the bit string (0 1) can be converted into the signal point arrangement xe2x80x983xe2x80x99, the bit string (1 1) can be converted into the signal point arrangement xe2x80x985xe2x80x99, and the bit string (1 0) can be converted into the signal point arrangement xe2x80x987xe2x80x99.
FIG. 9C shows the signal point arrangement when a BPSK modulation system is used. In the BPSK modulation system, a 1-bit digital signal (f) can be transmitted as 1 symbol. In the digital signal (f), for example, the bit (0) is converted into the signal point arrangement xe2x80x980xe2x80x99, and the bit (1) is converted into the signal point arrangement xe2x80x984xe2x80x99. The relationship between the signal point arrangement and the arrangement number in each modulation system is defined such that the signal point arrangement is equivalent to the arrangement number based on the 8 BPSK.
The I axis and the Q axis of the QPSK and the BPSK in the hierarchical transmission system match the I axis and the Q axis of the 8 PSK.
Eight frames shown in FIG. 8 form one superframe. In the area of 20 predetermined symbols of a frame synchronous signal pattern in each frame, a well-known 20-bit digital signal pattern (referred to as W1) is BPSK-mapped. In the area of 20 predetermined symbols of a superframe identification signal pattern as a leading frame in a superframe, a well-known 20-bit digital signal pattern (referred to as W2) different from W1 is BPSK-mapped. In the area of 20 predetermined symbols of a superframe identification signal pattern in each frame other than the leading frame in a superframe, a well-known 20-bit digital signal pattern (referred to as W3, and obtained by inverting each bit of W2) is BPSK-mapped.
In the receiver for receiving a digital modulated wave (PSK modulated wave) in the hierarchical transmission system, the intermediate frequency signal of a signal received by a reception circuit is demodulated through orthogonal detection by a demodulating circuit, thereby obtaining two sequences of I-Q base band signals (hereinafter, the I-Q base band signal can also be referred to as I-Q symbol stream data) indicating the momentary value for each symbol off the I axis and the Q axis orthogonal to each other. However, when there is a shift in phase between the carrier before the modulation of an input of the demodulating circuit and the reference carrier regenerated in the demodulating circuit, the received signal point of the modulated I-Q base band signal is phase-rotated toward the transmission side. Therefore, the digital signal transmitted on the transmission side cannot correctly recover if the data is input as it is to the decoder and PSK-mapped.
Each of the burst symbol signals (BS) shown in FIG. 8 is obtained by resetting the PN code generator having a predetermined configuration at the starting position of the initial burst symbol signal (BS) in a frame on the transmission side, shifting the output according to the symbol clock at each period in the transmission frame configuration, and performing a BPSK mapping process.
The demodulating circuit uses a burst symbol signal (BS) as a pilot signal for amendment of the phase of the reference carrier, and allows the phase of the carrier in the state before the modulation of the received signal to match the phase of the reference carrier, thereby setting the absolute phase such that the signal point of the I-Q base band signal output from the demodulating circuit as matching the signal point on the transmission side.
FIG. 10 shows, the configuration of the demodulating circuit of the receiver for receiving the PSK modulated wave in the conventional hierarchical transmission system. A demodulating circuit 1 shown in FIG. 10 obtains an I-Q base band signal by orthogonally detecting the intermediate frequency signal of a received signal. 10 denotes a carrier regeneration circuit for regenerating two reference carriers fc1 (=cos xcfx89t), and fc2 (=sin xcfx89t) whose frequencies and phases are synchronized with those of the carrier in the state before the modulation of the input of the demodulating circuit 1, and whose phases are 90xc2x0 shifted to each other to be orthogonal to each other. 2 and 3 denote multipliers for multiplying the intermediate frequency signal IF by the reference carriers fc1 and fc2. 4 and 5 denote A/D converters for A/D converting the output of the multipliers 2 and 3 at a sampling rate of double the symbol rate. 6 and 7 denote digital filters for limiting the band in a digital signal process performed on the output of the A/D converters 4 and 5. 8 and 9 denote thinning circuits for thinning the output of the digital filters 6 and 7 at the sampling rate of 1/2, and outputting two sequences of I-Q base band is signals (I-Q symbol stream data) indicating the momentary value of each symbol of the I axis and the Q axis. The thinning circuits 8 and 9 transmit the 1-Q base band signals I (8) and Q (8) (the numerals in the parentheses denote the numbers of quantization bits, which will be hereinafter referred to simply as I-Q for short) having 8 (complement of 2) quantization bits.
If the phase of a carrier in the state before modulation at the input of the demodulating circuit 1 matches the phase of the reference carriers fc1 and fc2 regenerated by the carrier regeneration circuit 10, then the phase of the received signal point in the I-Q phase by the I-Q base band signals I (8) and Q (8) on the reception side when the digital signal corresponding to the signal point arrangement xe2x80x980xe2x80x99 through xe2x80x987xe2x80x99 in the I-Q phase on the transmission side is received matches the phase on the transmission side. Therefore, the digital signal received from the signal point arrangement of the received signal point can be correctly identified by directly using the correspondence (refer to FIGS. 9A-9C) between the signal point arrangement on the transmission side and the digital signal.
However, since the reference carriers fc1 and fc2 can be actually in various phase states for the carrier in the state before the modulation of the input of the demodulating circuit 1, the received signal point on the reception side is the phase position set by turning from the position on the transmission side by a predetermined angle xcex8. When the phase of the carrier in the state before the modulation of the input of the demodulating circuit 1 is changed, the angle xcex8 is also changed. If the phase of the received signal point rotates at random from the phase on the transmission side, then the received digital signal cannot be identified. For example, at the time of xcex8=xcfx80/8, the digital signal (0 0 0) as the signal point arrangement xe2x80x980xe2x80x99 in the 8 PSK modulation system on the transmission side has the received signal point between the signal point arrangements xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 on the reception side. Therefore, if it is assumed that the digital signal (0 0 0) is received at the signal point arrangement xe2x80x980xe2x80x99, it is correctly received. However, if it is assumed that the signal is received at the signal point arrangement xe2x80x981xe2x80x99, it is mistakenly recognized that a digital signal (0 0 1) has been received. Then, the carrier regeneration circuit 10 amends the phase of the reference carriers fc1 and fc2 such that the received signal point can match the point on the transmission side to correctly identify the digital signal.
Specifically, the reference carrier fc1 is generated by oscillating a VCO (voltage control oscillator) 11 of the carrier regeneration circuit 10, and the reference carrier fc2 is generated by 90xc2x0 delaying the phase of the oscillation signal of the VCO 11 by a 90xc2x0 phase shifter 12. Then, the phase of the reference carriers fc1 and fc2 can be variable by varying the control voltage of the VCO 11.
In the carrier regeneration circuit 10, 13 and 14 are inverting circuits for selectively inverting the code of an I-Q base band signal output from the demodulating circuit 1 according to an output value of a well-known pattern regeneration circuit described later. 15 denotes a phase error table containing a phase error from an absolute phase for a received signal point in the state of the output of the inverting circuits, 13 and 14, and includes ROM. In this example, as described later, the absolute phase is fixed to 0 (=2xcfx80). FIG. 11 shows the relationship between the phase angle xcfx86 made by the received signal point of the I-Q phase in the state of the output of the inverting circuits 13 and 14 and the positive direction of the I axis and the phase error data xcex94xcfx86. The phase error data xcex94xcfx86 represents 8 quantization bits (complement of 2).
16 denotes a phase error detecting processing circuit for reading the phase error data xcex94xcfx86 (8) corresponding to the output of the inverting circuits 13 and 14 from the phase error table 15, and outputting it to a D/A converter 17. After the phase error data xcex94xcfx86 (8) is converted into a phase error voltage by the D/A converter 17, the lower band element is extracted by an LPF 18, and is applied as a control voltage to the VCO 11. If the phase error data xcex94xcfx86 (8) is 0, then an output of the LPF 18 is not changed, and the phases of the reference carriers fc1 and fc2 are not changed. However, if the phase error data xcex94xcfx86 (8) is positive (+), an output of the LPF 18 becomes large, the phases of the reference carriers fc1 and fc2 are delayed. On the other hand, if the phase error data xcex94xcfx86 (8) is negative (xe2x88x92), an output of the LPF 18 becomes small, and the phases of the reference carriers fc1 and fc2 are forwarded.
A timing circuit 30 is provided on the output side of the demodulating circuit 1, detects the starting timing in each symbol period corresponding to the frame synchronous signal pattern W1, and the superframe identification signal patterns W2 and W3 regardless of the existence/non-existence of the phase rotation as compared with the transmission side of the I-Q base band signal, and outputs timing signals T1 through T3. Furthermore, it detects a starting timing of the first burst symbol signal (BS) in a frame, and outputs a timing signal T4. In addition, it detects the period of the burst symbol signal (BS), and detects a period signal T5 indicating xe2x80x98Hxe2x80x99 for the period of the burst symbol signal, and xe2x80x98Lxe2x80x99 for other periods. Furthermore, it detects a symbol period corresponding to a superframe identification signal pattern W1, and a symbol period corresponding to superframe identification signal patterns W2 and W3, and outputs a period signal T6 indicating xe2x80x98Hxe2x80x99 for the above described periods and the period of the burst symbol signal (BS), and indicating xe2x80x98Lxe2x80x99 for other periods (refer to FIGS. 12 and 13).
40 denotes a pattern regeneration circuit, 41 denotes a frame synchronous signal pattern output circuit for outputting a 20-bit frame synchronous signal pattern W1 in the period of 20 symbols from the input timing of T1, 42 denotes a first superframe identification signal pattern output circuit for outputting a 20-bit superframe identification signal pattern W2 in the period of 20 symbols from the input timing of T2, 43 denotes a second superframe identification signal pattern output circuit for outputting a 20-bit superframe identification signal pattern W3 in the period of 20 symbols from the input timing of T3, 44 denotes a PN code generator, has the same configuration as the PN code generator for generating a PN code string for a burst symbol signal (BS) on the transmission side, changes its output according to a symbol clock while the period signal T5 indicates xe2x80x98Hxe2x80x99 after it is reset at the starting timing of the first burst symbol signal (BS) in the frame according to T4, and outputs the same pattern as the PN code pattern before the BPSK mapping of each burst symbol signal (BS) in the output of the demodulating circuit 1 at the same timing as the burst symbol signal (BS).
45 denotes an OR circuit for outputting a logical sum of the outputs of the frame synchronous signal pattern output circuit 41, the first superframe identification signal pattern output circuit 42, the second superframe identification signal pattern output circuit 43, and the PN code generator 44. 46 is an AND circuit for obtaining a logical product of the OR circuit 45 and the period signal T6.
The above described pattern regeneration circuit 40 regenerates a corresponding bit string pattern for the symbol corresponding to the 20-bit frame synchronous signal pattern W1 appearing in the I-Q symbol stream output from the demodulating circuit 1, the symbol corresponding to the 20-bit superframe identification signal patterns W2 and W3, and the burst symbol signal (BS). The W1, W2, and W3, and the PN code before the BPSK mapping of the burst symbol signal (BS) are well-known bit string patterns on the transmission side, and are BPSK-mapped. As shown in FIG. 9C, the bit 0 is mapped at the signal point arrangement xe2x80x980xe2x80x99 (absolute phase 0) on the transmission side, and the bit 1 is mapped at the signal point arrangement xe2x80x981xe2x80x99 (absolute phase xcfx80) on the transmission side.
The above described inverting circuits 13 and 14 respectively output the I-Q base band signals I (8) and Q (8) output from the demodulating circuit 1 as they are when the output of the pattern regeneration circuit 40 is a bit xe2x80x980xe2x80x99. At this time, the original absolute phase in the state on the transmission side of the received signal point indicated by the output RI (8)=I (8), RQ (8)=Q (8) is 0. On the other hand, the inverting circuits 13 and 14 inverts and outputs the code of the I-Q base band signal output from the demodulating circuit 1 when the output of the pattern regeneration circuit 40 is a bit xe2x80x981xe2x80x99. Inverting a code is forwarding the phase of a received signal point by xcfx80, and this indicates that the original absolute phase on the transmission side of the received signal point indicated by the outputs RI (8)=-I (8), and RQ (8)=-Q (8) of the inverting circuits 13 and 14 can also be assumed to be 0 (=2xcfx80).
The phase of then received signal point after demodulating the transmission signal BPSK-mapped at the bit xe2x80x980xe2x80x99 on the transmission side can be amended into 0 by reading the phase error data xcex94xcfx86 (8) corresponding to the output of the inverting circuits 13 and 14 from the phase error table 15 when the output of the pattern regeneration circuit 40 is xe2x80x980xe2x80x99, and amending the phases of the reference carriers fc1 and fc2 such that the phase error data xcex94xcfx86 (8) can be zero. Similarly, the phase of the received signal point after demodulating the transmission signal BPSK-mapped at the bit xe2x80x980xe2x80x99 on the transmission side can be amended into xcfx80 by reading the phase error data xcex94xcfx86 (8) corresponding to the output of the inverting circuits 13 and 14 from the phase error table 15 when the output of the pattern regeneration circuit 40 is xe2x80x981xe2x80x99, and amending the phases of the reference carriers fc1 and fc2 such that the phase error data xcex94xcfx86 (8) can be zero. Therefore, the demodulating circuit 1 can output an absolute-phase I-Q base band signal, and the decoder at a later stage can perform a PSK demapping process without fail.
The D/A converter 17 D/A converts and outputs the phase error data xcex94xcfx86 (8) in the period only when the period signal T6 at the H level is input from the timing circuit 30. While the T6 indicates the L level, the D/A converter 17 holds the last output value obtained when the T6 indicated the H level immediately before.
However, in the conventional receiver described above, it is necessary to define a phase error table for the entire range from the first quadrant to the fourth quadrant in the I-Q phase indicated by the outputs of the inverting circuits 13 and 14, thereby causing the problem of large memory requirements.
The present invention aims at providing a demodulating apparatus of a receiver requiring only a small circuit.
The demodulating apparatus according to claim 1 for use in a receiver having a demodulating unit for demodulating a PSK modulated signal obtained by time-multiplexing digital signals modulated in various PSK modulation systems by using a carrier regenerated by a carrier regeneration unit, and outputting I-Q symbol stream data in a symbol unit includes: regeneration means for regenerating a digital signal of a predetermined pattern for a 2-phase modulated portion in the output of the demodulating means on the transmission side; inverting means for selectively code-inverting the I-Q symbol stream data output from the demodulating unit based on the value of a predetermined pattern regenerated by the regeneration means; a phase error table showing the phase error from the absolute phase for the received signal point in a predetermined quadrant; and phase error detecting means for converting a received signal point in the I-Q phase indicated by an output of the inverting unit into the one in a predetermined quadrant by performing a process depending on the current quadrant, reading the phase error data corresponding to the converted received signal point from the phase error table, and adjusting the read phase error data depending on the conversion. With the configuration, the carrier regeneration means amends the phase of the regenerated carrier according to the phase error data adjusted by the phase error detecting means.
The PSK modulated signal obtained by time-multiplexing the digital signal modulated in the 2-phase, 4-phase, and 8-phase PSK modulation system is demodulated using a carrier regenerated by the carrier regeneration means, and output as the I-Q symbol stream data in a symbol unit by the demodulating unit. The regeneration unit regenerates a well-known pattern for the portion obtained by 2-phase modulating the digital signal of the well-known pattern on the transmission side in the output of the demodulating unit, and the inverting unit selectively code-inverts the I-Q symbol stream data output from the demodulating means based on the value of the well-known pattern. The phase error table contains a phase error from the absolute phase for the received signal point in a predetermined quadrant in the I-Q phases indicated by the output of the inverting means. The phase error detecting means performs a process by combining any of the no-conversion process, the symmetric conversion about the I axis, the symmetric conversion about the Q axis, the symmetric conversion about the I=Q axis, and the symmetric conversion about the I=-Q axis, reads from the phase error table the phase error data corresponding to the received signal point converted in the predetermined quadrant defined in the phase error table, adjusts the read phase error data based on the combination of the conversion, and obtains the phase error data from the absolute phase for the received signal point in the I-Q phase indicated by an output of the inverting means. The carrier regeneration means amends the phase of the regenerated carrier based on the phase error data detected by the phase error detecting means.
According to the present invention, the phase error table can contain a phase error from the absolute phase for the received signal point in a predetermined quadrant in the first through the fourth quadrants in the I-Q phase, thereby considerably simplifying the circuit configuration.